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MCP453X/455X/463X/465X
7/8-Bit Single/Dual I2C Digital POT with Volatile Memory
Features
* Single or Dual Resistor Network options * Potentiometer or Rheostat configuration options * Resistor Network Resolution - 7-bit: 128 Resistors (129 Steps) - 8-bit: 256 Resistors (257 Steps) * RAB Resistances options of: - 5 k - 10 k - 50 k - 100 k * Zero-Scale to Full-Scale Wiper operation * Low Wiper Resistance: 75 (typical) * Low Tempco: - Absolute (Rheostat): 50 ppm typical (0C to 70C) - Ratiometric (Potentiometer): 15 ppm typical * I2C Serial interface - 100 kHz, 400 kHz and 3.4 MHz support * Serial protocol allows: - High-Speed Read/Write to wiper - Increment/Decrement of wiper * Resistor Network Terminal Disconnect Feature via the Terminal Control (TCON) Register * Brown-out reset protection (1.5V typical) * Serial Interface Inactive current (2.5 uA typical) * High-Voltage Tolerant Digital Inputs: Up to 12.5V * Wide Operating Voltage: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation * Wide Bandwidth (-3dB) Operation: - 2 MHz (typical) for 5.0 k device * Extended temperature range (-40C to +125C)
Description
The MCP45XX and MCP46XX devices offer a wide range of product offerings using an I2C interface. This family of devices support 7-bit and 8-bit resistor networks, Volatile memory configurations, and Potentiometer and Rheostat pinouts.
Package Types (top view)
MCP45X1 Single Potentiometer
HVC / A0 SCL SDA VSS 1 2 3 4 8 7 6 5 VDD P0B P0W P0A
MCP45X2 Single Rheostat
HVC / A0 SCL SDA VSS 1 2 3 4 8 7 6 5 VDD A1 P0B P0W
MSOP
HVC / A0 1 SCL 2 SDA 3 VSS 4 EP 9 8 VDD 7 A1 6 P0B 5 P0W HVC / A0 1 SCL 2 SDA 3 VSS 4
MSOP
8 VDD EP 9 7 A1 6 P0B 5 P0W
DFN 3x3 (MF) *
DFN 3x3 (MF) *
MCP46X1 Dual Potentiometers
HVC/A0 SCL SDA VSS P1B P1W P1A 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD A1 A2 NC P0B P0W P0A HVC/A0 VDD A1 A2 16 15 14 13 SCL SDA VSS VSS 1 2 3 4 EP 17 5678 P1B P1W P1A P0A 12 NC 11 NC 10 P0B 9 P0W
TSSOP
QFN-16 4x4 (ML) * MCP46X2 Dual Rheostat
HVC/A0 SCL SDA VSS P1B 1 2 3 4 5 10 VDD HVC / A0 1 9 A1 SCL 2 8 P0B SDA 3 7 P0W VSS 4 6 P1W P1B 5 10 VDD EP 11 9 8 7 6 A1 P0B P0W P1W
MSOP
DFN 3x3 (MF) *
* Includes Exposed Thermal Pad (EP); see Table 3-1.
(c) 2008 Microchip Technology Inc.
DS22096A-page 1
MCP453X/455X/463X/465X
Device Block Diagram
VDD VSS A2 A1 HVC/A0 SCL SDA 2 I C Interface Power-up/ Brown-out Control I2C Serial Interface Module & Control Logic (WiperLockTM Technology) P0A
Resistor Network 0 (Pot 0) Wiper 0 & TCON Register
P0W
P0B P1A
Resistor Network 1 (Pot 1) Wiper 1 & TCON Register
P1W
Memory (16x9) Wiper0 (V & NV) Wiper1 (V & NV) TCON Reserved
P1B
For Dual Resistor Network Devices Only
Device Features
WiperLock Technology POR Wiper Setting # of Steps # of POTs Control Interface Memory Type Resistance (typical) RAB Options (k) Wiper - RW () 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 Wiper Configuration VDD Operating Range (2)
Device
MCP4531 (3) MCP4532 (3) MCP4541 MCP4542 MCP4551 (3) MCP4552 (3) MCP4561 MCP4562 MCP4631 (3) MCP4632 (3) MCP4641 MCP4642 MCP4651 (3) MCP4652 (3) MCP4661 MCP4662 Note 1: 2: 3:
1 Potentiometer (1) 1 1 1 1 1 1 1 2 2 2 2 2 2 Rheostat Potentiometer (1) Rheostat Potentiometer (1) Rheostat Potentiometer (1) Rheostat
(1)
I2C I2C I2C I2C I2C I2C I2C I2C IC I2C I2C I2C I2C I2C IC I2C
2 2
RAM RAM EE EE RAM RAM EE EE RAM RAM EE EE RAM RAM EE EE
No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes
Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0
129 1.8V to 5.5V 129 1.8V to 5.5V 129 2.7V to 5.5V 129 2.7V to 5.5V 257 1.8V to 5.5V 257 1.8V to 5.5V 257 2.7V to 5.5V 257 2.7V to 5.5V 129 1.8V to 5.5V 129 1.8V to 5.5V 129 2.7V to 5.5V 129 2.7V to 5.5V 257 1.8V to 5.5V 257 1.8V to 5.5V 257 2.7V to 5.5V 257 2.7V to 5.5V
2 Potentiometer Rheostat
Potentiometer (1) Rheostat Potentiometer (1) Rheostat
(1)
2 Potentiometer Rheostat
Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. Please check Microchip web site for device release and availability
DS22096A-page 2
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Voltage on VDD with respect to VSS ............... -0.6V to +7.0V Voltage on HVC/A0, A1, A2, SCL, and SDA with respect to VSS ............................................................................. -0.6V to 12.5V Voltage on all other pins (PxA, PxW, and PxB) with respect to VSS ......................................... -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins) ......................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ..................................................20 mA Maximum output current sunk by any Output pin ......................................................................................25 mA Maximum output current sourced by any Output pin ......................................................................................25 mA Maximum current out of VSS pin .................................100 mA Maximum current into VDD pin ....................................100 mA Maximum current into PXA, PXW & PXB pins ............2.5 mA Storage temperature ....................................-65C to +150C Ambient temperature with power applied -40C to +125C Total power dissipation (Note 1) ................................400 mW Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins .................................. 4 kV (HBM), .......................................................................... 300V (MM) Maximum Junction Temperature (TJ) ......................... +150C
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
(c) 2008 Microchip Technology Inc.
DS22096A-page 3
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VDD VHV Min 2.7 1.8 HVC pin Voltage Range VSS VSS VDD Start Voltage to ensure Wiper Reset VDD Rise Rate to ensure Power-on Reset Delay after device exits the reset state (VDD > VBOR) Supply Current (Note 10) VBOR -- Typ -- -- -- -- -- Max 5.5 2.7 12.5V VDD + 8.0V 1.65 Units V V V V V Serial Interface only. VDD The HVC pin will be at one 4.5V of three input levels V < (VIL, VIH or VIHH). (Note 6)
DD
Parameters Supply Voltage
Conditions
4.5V RAM retention voltage (VRAM) < VBOR
VDDRR
(Note 9)
V/ms
TBORD
--
10
20
s
IDD
--
--
600
A
Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11) Write all 0's to Volatile Wiper 0 VDD = 5.5V, FSCL = 3.4 MHz Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11) Write all 0's to Volatile Wiper 0 VDD = 5.5V, FSCL = 100 kHz Serial Interface Inactive, (Stop condition, SCL = SDA = VIH), Wiper = 0 VDD = 5.5V, HVC/A0 = VIH
--
--
250
A
--
2.5
5
A
Note 1: 2: 3: 4: 5: 6: 7:
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
DS22096A-page 4
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym RAB Min 4.0 8.0 40.0 80.0 Resolution Step Resistance N RS -- -- Nominal Resistance Match |RAB0 - RAB1| / RAB |RBW0 - RBW1| / RBW Wiper Resistance (Note 3, Note 4) Nominal Resistance Tempco Ratiometeric Tempco Resistor Terminal Input Voltage Range (Terminals A, B and W) Note 1: 2: 3: 4: 5: 6: 7: RW RAB/T -- -- -- -- -- -- -- VWB/T VA,VW,VB -- Vss Typ 5 10 50 100 257 129 RAB / (256) RAB / (128) 0.2 0.25 75 75 50 100 150 15 -- -- -- 1.25 1.5 160 300 -- -- -- -- VDD Max 6.0 12.0 60.0 120.0 Units k k k k Taps Taps % % Conditions -502 devices (Note 1) -103 devices (Note 1) -503 devices (Note 1) -104 devices (Note 1) 8-bit 7-bit 8-bit 7-bit No Missing Codes No Missing Codes Note 6 Note 6
Parameters Resistance ( 20%)
MCP46X1 devices only MCP46X2 devices only, Code = Full-Scale VDD = 5.5 V, IW = 2.0 mA, code = 00h VDD = 2.7 V, IW = 2.0 mA, code = 00h
ppm/C TA = -20C to +70C ppm/C TA = -40C to +85C ppm/C TA = -40C to +125C ppm/C Code = Midscale (80h or 40h) V Note 5, Note 6
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
(c) 2008 Microchip Technology Inc.
DS22096A-page 5
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym IT Min -- -- -- -- Typ -- -- -- -- Max 2.5 2.5 2.5 1.38 Units mA mA mA mA Terminal A Terminal B Terminal W Conditions
IAW, W = Full-Scale (FS) IBW, W = Zero Scale (ZS) IAW or IBW, W = FS or ZS IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 4000
Parameters Maximum current through Terminal (A, W or B) Note 6
--
--
0.688
mA Terminal A and Terminal B
IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 8000 IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 40000 IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 80000
--
--
0.138
mA
--
--
0.069
mA
Leakage current into A, W or B
IWL
-- -- --
100 100 100
-- -- --
nA nA nA
MCP4XX1 PxA = PxW = PxB = VSS MCP4XX2 PxB = PxW = VSS Terminals Disconnected (R1HW = R0HW = 0)
Note 1: 2: 3: 4: 5: 6: 7:
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
DS22096A-page 6
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VWFSE Min -6.0 -4.0 -3.5 -2.0 -0.8 -0.5 -0.5 -0.5 Zero-Scale Error (MCP4XX1 only) (8-bit code = 00h, 7-bit code = 00h) VWZSE -- -- -- -- -- -- -- -- Potentiometer Integral Non-linearity Potentiometer Differential Non-linearity Note 1: 2: 3: 4: 5: 6: 7: INL -1 -0.5 DNL -0.5 -0.25 Typ -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 0.5 0.25 0.25 0.125 Max -- -- -- -- -- -- -- -- +6.0 +3.0 +3.5 +2.0 +0.8 +0.5 +0.5 +0.5 +1 +0.5 +0.5 +0.25 Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb 8-bit 7-bit 8-bit 7-bit 50 k 10 k 5 k 50 k 10 k 5 k 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 100 k 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 100 k 8-bit 7-bit Conditions 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V
Parameters Full-Scale Error (MCP4XX1 only) (8-bit code = 100h, 7-bit code = 80h)
3.0V VDD 5.5V MCP4XX1 devices only (Note 2) 3.0V VDD 5.5V MCP4XX1 devices only (Note 2)
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
(c) 2008 Microchip Technology Inc.
DS22096A-page 7
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym BW Min -- -- -- -- -- -- -- -- Note 1: 2: 3: 4: 5: 6: 7: Typ 2 2 1 1 200 200 100 100 Max -- -- -- -- -- -- -- -- Units MHz MHz MHz MHz kHz kHz kHz kHz 50 k 10 k 5 k 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 100 k 8-bit 7-bit Conditions Code = 80h Code = 40h Code = 80h Code = 40h Code = 80h Code = 40h Code = 80h Code = 40h
Parameters Bandwidth -3 dB (See Figure 2-65, load = 30 pF)
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
DS22096A-page 8
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym R-INL Min -1.5 -8.25 -1.125 -6.0 -1.5 -5.5 -1.125 -4.0 -1.5 -2.0 -1.125 -1.5 -1.0 -1.5 -0.8 -1.125 Note 1: 2: 3: 4: 5: 6: 7: Typ 0.5 +4.5 0.5 +4.5 0.5 +2.5 0.5 +2.5 0.5 +1 0.5 +1 0.5 +0.25 0.5 +0.25 Max +1.5 +8.25 +1.125 +6.0 +1.5 +5.5 +1.125 +4.0 +1.5 +2.0 +1.125 +1.5 +1.0 +1.5 +0.8 +1.125 Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb 7-bit 100 k 8-bit 7-bit 50 k 8-bit 7-bit 10 k 8-bit 7-bit 5 k 8-bit Conditions 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7)
Parameters Rheostat Integral Non-linearity MCP45X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4)
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
(c) 2008 Microchip Technology Inc.
DS22096A-page 9
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym R-DNL Min -0.5 -1.0 -0.375 -0.75 -0.5 -1.0 -0.375 -0.75 -0.5 -0.5 -0.375 -0.375 -0.5 -0.5 -0.375 -0.375 Capacitance (PA) Capacitance (Pw) Capacitance (PB) Note 1: 2: 3: 4: 5: 6: 7: CAW CW CBW -- -- -- Typ 0.25 +0.5 0.25 +0.5 0.25 +0.25 0.25 +0.5 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 75 120 75 Max +0.5 +1.0 +0.375 +0.75 +0.5 +1.0 +0.375 +0.75 +0.5 +0.5 +0.375 +0.375 +0.5 +0.5 +0.375 +0.375 -- -- -- Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb pF pF pF 7-bit 100 k 8-bit 7-bit 50 k 8-bit 7-bit 10 k 8-bit 7-bit 5 k 8-bit Conditions 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) f =1 MHz, Code = Full-Scale f =1 MHz, Code = Full-Scale f =1 MHz, Code = Full-Scale
Parameters Rheostat Differential Non-linearity MCP45X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4)
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
DS22096A-page 10
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VIH Min 0.45 VDD Typ -- Max -- Units V All Inputs except SDA and SCL SDA and SCL Conditions 2.7V VDD 5.5V (Allows 2.7V Digital VDD with 5V Analog VDD) 1.8V VDD 2.7V
Parameters Schmitt Trigger High Input Threshold
Digital Inputs/Outputs (SDA, SCK, HVC/A0, A1, A2, WP)
0.5 VDD
--
--
V
0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD Schmitt Trigger Low Input Threshold VIL -- -0.5 -0.5 -0.5 -0.5 Hysteresis of Schmitt Trigger Inputs (Note 6) VHYS -- N.A. N.A. 0.1 VDD 0.05 VDD 0.1 VDD 0.1 VDD High Voltage Limit Note 1: 2: 3: 4: 5: 6: 7: VMAX --
-- -- -- -- -- -- -- -- -- 0.1VDD -- -- -- -- -- -- --
VMAX VMAX VMAX VMAX 0.2VDD 0.3VDD 0.3VDD 0.3VDD 0.3VDD -- -- -- -- -- -- -- 12.5 (6)
V V V V V V V V V V V V V V V V V SDA and SCL SDA and SCL
100 kHz 400 kHz 1.7 MHz 3.4 Mhz All inputs except SDA and SCL 100 kHz 400 kHz 1.7 MHz 3.4 Mhz All inputs except SDA and SCL 100 kHz 400 kHz 1.7 MHz 3.4 Mhz Pin can tolerate VMAX or less. VDD < 2.0V VDD 2.0V VDD < 2.0V VDD 2.0V
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
(c) 2008 Microchip Technology Inc.
DS22096A-page 11
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VOL IPU Min VSS VSS -- -- HVC Pull-up / Pull-down Resistance Input Leakage Current Pin Capacitance RAM (Wiper) Value Value Range TCON POR/BOR Value Power Requirements Power Supply Sensitivity (MCP45X2 and MCP46X2 only) Note 1: 2: 3: 4: 5: 6: 7: PSS -- -- 0.0015 0.0015 0.0035 0.0035 %/% %/% 8-bit 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h N NTCON 0h 0h -- -- 1FFh 1FFh 1FFh hex hex hex 8-bit device 7-bit device All Terminals connected RHVC -- Typ -- -- -- 170 16 Max 0.2VDD 0.4 1.75 -- -- Units V V mA A k Conditions VDD < 2.0V, IOL = 1 mA VDD 2.0V, IOL = 3 mA Internal VDD pull-up, VIHH pull-down VDD = 5.5V, VIHH = 12.5V HVC pin, VDD = 5.5V, VHVC = 3V VDD = 5.5V, VHVC = 3V
Parameters Output Low Voltage (SDA) Weak Pull-up / Pull-down Current
IIL CIN, COUT
-1 --
-- 10
1 --
A pF
VIN = VDD and VIN = VSS fC = 3.4 MHz
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification
DS22096A-page 12
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
SCL 90 SDA
91 92
93
START Condition
STOP Condition
FIGURE 1-1: TABLE 1-1:
I2C Bus Start/Stop Bits Timing Waveforms. I2C BUS START/STOP BITS REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Characteristic Standard Mode Fast Mode High-Speed 1.7 High-Speed 3.4 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode Min 0 0 0 0 -- -- -- -- 4700 600 160 160 4000 600 160 160 4000 600 160 160 4000 600 160 160 Max 100 400 1.7 3.4 400 400 400 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units kHz kHz MHz MHz pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Cb = 400 pF, 1.8V - 5.5V Cb = 400 pF, 2.7V - 5.5V Cb = 400 pF, 4.5V - 5.5V Cb = 100 pF, 4.5V - 5.5V
I2C AC Characteristics
Param. Symbol No. FSCL
D102
Cb
Bus capacitive loading
90
TSU:STA
START condition Setup time
Only relevant for repeated START condition
91
THD:STA
START condition Hold time
After this period the first clock pulse is generated
92
TSU:STO
STOP condition Setup time
93
THD:STO STOP condition Hold time
(c) 2008 Microchip Technology Inc.
DS22096A-page 13
MCP453X/455X/463X/465X
103 SCL SDA In 109 SDA Out 109 110 100 101 90 91 106 107 92 102
FIGURE 1-2: TABLE 1-2:
I2C Bus Data Timing. I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Min 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 4000 600 120 60 4700 1300 320 160 -- -- -- -- Max -- -- Units ns ns ns ns ns ns ns ns Conditions 1.8V-5.5V 2.7V-5.5V 4.5V-5.5V 4.5V-5.5V 1.8V-5.5V 2.7V-5.5V 4.5V-5.5V 4.5V-5.5V
I2C AC Characteristics
Param. No. 100
Sym THIGH
Characteristic Clock high time
101
TLOW
Clock low time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
Note 1: 2:
3:
4: 5: 6: 7:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test.
DS22096A-page 14
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Min 100 kHz mode 400 kHz mode 1.7 MHz mode 1.7 MHz mode -- 20 + 0.1Cb 20 20 Max 1000 300 80 160 Units ns ns ns ns Conditions Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) After a Repeated Start condition or an Acknowledge bit After a Repeated Start condition or an Acknowledge bit Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) I2C AC Characteristics
Param. No. 102A (5)
Sym TRSCL
Characteristic SCL rise time
3.4 MHz mode 3.4 MHz mode
10 10
40 80
ns ns
102B (5)
TRSDA
SDA rise time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
-- 20 + 0.1Cb 20 10 -- 20 + 0.1Cb 20 10 -- 20 + 0.1Cb (4) 20 10 0 0 0 0
1000 300 160 80 300 300 80 40 300 300 160 80 -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
103A
(5)
TFSCL
SCL fall time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode)
103B
(5)
TFSDA
SDA fall time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode)
106
THD:DAT
Data input hold time
100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode
1.8V-5.5V, Note 6 2.7V-5.5V, Note 6 4.5V-5.5V, Note 6 4.5V-5.5V, Note 6
Note 1: 2:
3:
4: 5: 6: 7:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test.
(c) 2008 Microchip Technology Inc.
DS22096A-page 15
MCP453X/455X/463X/465X
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Min 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 109 TAA Output valid from clock 100 kHz mode 400 kHz mode 1.7 MHz mode 250 100 10 10 -- -- -- -- 3.4 MHz mode 110 TBUF Bus free time 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode TSP Input filter spike suppression (SDA and SCL) 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode Note 1: 2: -- 4700 1300 N.A. N.A. -- -- -- -- Max -- -- -- -- 3450 900 150 310 150 -- -- -- -- 50 50 10 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Spike suppression Spike suppression Philips Spec states N.A. Cb = 100 pF, Note 1, Note 7 Cb = 400 pF, Note 1, Note 5 Cb = 100 pF, Note 1 Time the bus must be free before a new transmission can start Note 1 Note 2 Conditions I2C AC Characteristics
Param. No. 107
Sym
Characteristic
TSU:DAT Data input setup time
3:
4: 5: 6: 7:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test.
DS22096A-page 16
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-DFN (3x3) Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-SOIC Thermal Resistance, 10L-DFN (3x3) Thermal Resistance, 10L-MSOP Thermal Resistance, 14L-MSOP Thermal Resistance, 14L-SOIC Thermal Resistance, 16L-QFN JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 60 211 145.5 57 202 N/A 95.3 47 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Sym Min Typ Max Units Conditions
(c) 2008 Microchip Technology Inc.
DS22096A-page 17
MCP453X/455X/463X/465X
NOTES:
DS22096A-page 18
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
450 400 300 IDD (uA) 250 200 150 100 50 0 -40 0 40 Temperature (C) 80 120 350
250
3.4MHz, 5.5V
RHVC (kOhms)
3.4MHz, 2.7V
200
1.7MHz, 5.5V
150 100 50
RHVC
IHVC
1.7MHz, 2.7V
400kHz, 5.5V 100kHz, 5.5V
400kHz, 2.7V
100kHz, 2.7V
0 2 3 4 5 6 7 VHVC (V) 8 9 10
1000 800 600 400 200 0 -200 -400 -600 -800 -1000
FIGURE 2-1: Device Current (IDD) vs. I2C Frequency (fSCL) and Ambient Temperature (VDD = 2.7V and 5.5V).
3
FIGURE 2-4: HVC Pull-up/Pull-down Resistance (RHVC) and Current (IHVC) vs. HVC Input Voltage (VHVC) (VDD = 5.5V).
12 HVC VPP Threshold (V) 10
5.5V Entry
2.5 Istandby (uA) 2 1.5 1 2.7V 0.5 -40 0 40 Temperature (C) 80 120 5.5V
8 6 4
2.7V Exit 5.5V Exit
2.7V Entry
2 0 -40 -20 0 20 40 60 80 Ambient Temperature (C) 100 120
FIGURE 2-2: Device Current (ISHDN) and VDD. (HVC = VDD) vs. Ambient Temperature.
420 400 IWRITE (A) 380 360 5.5V 340 320 300 -40 0 40 Temperature (C) 80 120
FIGURE 2-5: HVC High Input Entry/Exit Threshold vs. Ambient Temperature and VDD.
FIGURE 2-3: Write Current (IWRITE) vs. Ambient Temperature.
(c) 2008 Microchip Technology Inc.
DS22096A-page 19
IHVC (A)
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (R W) (ohms) 100 80 0 60 -0.1 40
125C 85C -40C 25C RW
0.2 Error (LSb) 0.1
Wiper Resistance (R W) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3
120 100 80 60 40
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
1.25 0.75 0.25 -0.25 Error (LSb)
Error (LSb)
DNL
INL
INL
-0.2
125C
85C 25C
-40C
DNL
-0.75
RW
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-1.25 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-6: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 0 140 100 60
-40C 25C 85C RW 125C
FIGURE 2-9: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 140
RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
6 4 2 0
INL DNL
INL
-0.1 -0.2
100 60 20 0
125C 85C -40C 25C DNL
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
32
-2 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-7: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
0.5 0.4 0.3 0.2 1500 1000 500
RW DNL
FIGURE 2-10: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
118 98 78 58 38
Wiper Resistance (RW) (ohms)
Wiper Resistance (RW) (ohms)
2500 2000
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
2500 2000 1500 1000 500
INL
INL
0.1 0
-0.1 -0.2 -0.3 0 64 128 192 Wiper Setting (decimal) 256
Error (LSb)
RW
DNL
18 -2
0
0 0 64 128 192 Wiper Setting (decimal) 256
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
FIGURE 2-8: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-11: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
DS22096A-page 20
(c) 2008 Microchip Technology Inc.
Error (LSb)
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
5300 Nominal Resistance (R AB) (Ohms) 5250 RWB (Ohms)
2.7V
6000 5000 4000 3000 2000 1000 0
-40C 25C 85C 125C
5200 5150 5100
5.5V
5050 -40 0 40 80 Ambient Temperature (C) 120
0
32
64 96 128 160 192 Wiper Setting (decimal)
224
256
FIGURE 2-12: 5 k - Nominal Resistance () vs. Ambient Temperature and VDD.
FIGURE 2-13: 5 k - RWB () vs. Wiper Setting and Ambient Temperature.
(c) 2008 Microchip Technology Inc.
DS22096A-page 21
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-14: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-17: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-15: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-18: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-16: 5 k - Power-Up Wiper Response Time (20 ms/Div).
DS22096A-page 22
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (R W) (ohms) 100 80 0 60 -0.1 40 20 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal)
25C -40C 125C 85C RW
0.2 Error (LSb) 0.1
Wiper Resistance (R W) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3
120 100 80
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
1
0.5 Error (LSb)
Error (LSb)
INL
DNL
INL
0 60 40
125C -40C RW DNL
-0.5
-0.2 -0.3
85C 25C
20 0 32
-1 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-19: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 0 140 100 60 20 0
25C 125C 85C -40C RW
FIGURE 2-22: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 1 140 100 60
125C 85C 25C -40C DNL RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
4 3 Error (LSb) 2
INL
DNL
INL
-0.1 -0.2
0 -1 -2 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal)
32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20
FIGURE 2-20: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
0.6
FIGURE 2-23: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
4000 Wiper Resistance (R W)(ohms) 3500 3000 2500 2000 1500 1000 500 0 0
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
4000 3500 3000 2500 2000 1500 1000 500 0 0
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 Error (LSb)
INL
INL
DNL
RW
RW
DNL
64 128 192 Wiper Setting (decimal)
-0.3 256
98 88 78 68 58 48 38 28 18 8 -2
64 128 192 Wiper Setting (decimal)
256
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
FIGURE 2-21: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-24: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
(c) 2008 Microchip Technology Inc.
DS22096A-page 23
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
10300
AB)
12000 10000
10250 10200 10100 10050 10000 9950 9900 9850 -40 0 40 80 Ambient Temperature (C) 120
1.8V
Nominal Resistance (R (Ohms)
RWB (Ohms)
10150
2.7V
8000 6000 4000 2000 0 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256
-40C 25C 85C 125C
5.5V
FIGURE 2-25: 10 k - Nominal Resistance () vs. Ambient Temperature and VDD.
FIGURE 2-26: 10 k - RWB () vs. Wiper Setting and Ambient Temperature.
DS22096A-page 24
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-27: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-30: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-28: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-31: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-29: 10 k - Power-Up Wiper Response Time (1 s/Div).
(c) 2008 Microchip Technology Inc.
DS22096A-page 25
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (R W) (ohms) 100 80 0 60 -0.1 40
125C 25C 85C -40C RW
0.2 Error (LSb) 0.1
Wiper Resistance (R W) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3
120 100 80
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb)
Error (LSb)
DNL
INL
INL DNL
0.1 0
60 -0.1 40
125C 85C 25C -40C RW
-0.2
-0.2
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-32: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 0 140 100 60 20 0
125C 85C 25C -40C RW
FIGURE 2-35: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 140 100 60
125C -40C 85C 25C RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 Error (LSb)
INL DNL
DNL
INL
-0.1 -0.2
32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32 64
-1 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-33: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
15000 14000 13000 12000 11000 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 0 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 256
FIGURE 2-36: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
15000 14000 13000 12000 11000 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
Wiper Resistance (RW) (ohms)
Wiper Resistance (Rw) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
RW INL
INL RW
Error (LSb)
DNL
DNL
78.5 73.5 68.5 63.5 58.5 53.5 48.5 43.5 38.5 33.5 28.5 23.5 18.5 13.5 8.5 3.5 -1.5
64 128 192 Wiper Setting (decimal)
0 25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
FIGURE 2-34: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-37: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
DS22096A-page 26
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
52500
AB)
60000 50000
52000 RWB (Ohms) 51500 51000 50500 50000 49500 49000 -40 0 40 80 Ambient Temperature (C) 120
2.7V 5.5V 1.8V
Nominal Resistance (R (Ohms)
40000 30000 20000 10000 0
-40C 25C 85C 125C
0
32
64 96 128 160 192 Wiper Setting (decimal)
224
256
FIGURE 2-38: 50 k - Nominal Resistance () vs. Ambient Temperature and VDD.
FIGURE 2-39: 50 k - RWB () vs. Wiper Setting and Ambient Temperature.
(c) 2008 Microchip Technology Inc.
DS22096A-page 27
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-40: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-43: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-41: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-44: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-42: 50 k - Power-Up Wiper Response Time (1 s/Div).
DS22096A-page 28
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (R W) (ohms) 100 80 60 40 20 0 32 -0.1
25C -40C 125C 85C RW
Wiper Resistance (R W) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.2
120 100 80 60
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb)
Error (LSb)
Error (LSb)
INL DNL
0.1
INL DNL
0.1 0 -0.1
0
40
125C 85C 25C
-40C
RW
-0.2
-0.2 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-45: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 140 100 60 20 0
125C 85C 25C -40C RW
FIGURE 2-48: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (Rw) (ohms) 260 220 180 0 140 100 60 20 0
125C 85C 25C -40C RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.2 0.15 0.1 0.05 0 Error (LSb)
0.6 0.4 Error (LSb) 0.2
INL DNL
INL DNL
-0.05 -0.1 -0.15
-0.2 -0.4
32
-0.2 64 96 128 160 192 224 256 Wiper Setting (decimal)
32
-0.6 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-46: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
0.35
FIGURE 2-49: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
Wiper Resistance (RW) (ohms)
Wiper Resistance (RW) (ohms)
25000 20000 15000 10000 5000
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.25
25000 20000
RW INL
0.05
Error (LSb)
DNL
0.15
15000 10000 5000
DNL
-0.05 -0.15
RW INL
-0.25 -0.35
0 0 64 128 192 Wiper Setting (decimal)
0 0 64 128 192 Wiper Setting (decimal) 256
59 54 49 44 39 34 29 24 19 14 9 4 -1
256
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
Note:
Refer to AN1080 for additional information on the characteristics of the wiper resistance (RW) with respect to device voltage and wiper setting value.
FIGURE 2-47: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
FIGURE 2-50: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 1.8V).
(c) 2008 Microchip Technology Inc.
DS22096A-page 29
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
103500 103000 102500 102000 101500 101000 100500 100000 99500 99000 98500 -40
120000 100000
Nominal Resistance (R (Ohms)
AB)
Rwb (Ohms)
80000 60000 40000 20000
-40C 25C 85C 125C
1.8V
2.7V 5.5V
0
0 40 80 Ambient Temperature (C)
120
0
32
64
96 128 160 192 Wiper Setting (decimal)
224
256
FIGURE 2-51: 100 k - Nominal Resistance () vs. Ambient Temperature and VDD .
FIGURE 2-52: 100 k - RWB () vs. Wiper Setting and Ambient Temperature.
DS22096A-page 30
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-53: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-55: 100 k - Low-Voltage Increment Wiper Settling Time (VDD =5.5V) (1 s/Div).
FIGURE 2-54: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-56: 100 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div)
(c) 2008 Microchip Technology Inc.
DS22096A-page 31
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
0.12 0.1
5.5V
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 -40
0.08
%
5.5V
%
0.06 0.04 0.02 0
3.0V
3.0V
0
40 80 Temperature (C)
120
-40
0
40 80 Temperature (C)
120
FIGURE 2-57: Resistor Network 0 to Resistor Network 1 RAB (5 k) Mismatch vs. VDD and Temperature.
FIGURE 2-59: Resistor Network 0 to Resistor Network 1 RAB (50 k) Mismatch vs. VDD and Temperature.
0.04 0.03 0.02 0.01 % 0 -0.01 -0.02 -0.03 -0.04 -40 0 40 80 Temperature (C) 120
3.0V 5.5V
0.05 0.04 0.03 0.02
%
5.5V
0.01 0 -0.01 -0.02 -0.03 -40 10 60 Temperature (C) 110
3.0V
FIGURE 2-58: Resistor Network 0 to Resistor Network 1 RAB (10 k) Mismatch vs. VDD and Temperature.
FIGURE 2-60: Resistor Network 0 to Resistor Network 1 RAB (100 k) Mismatch vs. VDD and Temperature.
DS22096A-page 32
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
4 3.5
5.5V
230 210 190 VOL (mV) 170 150 130 110 90 70 50 -40 0 40 Temperature (C) 80 120 -40 0 40 Temperature (C) 80 120
5.5V 2.7V
3 VIH (V) 2.5 2 1.5 1
2.7V
FIGURE 2-61: Temperature.
2
VIH (SDA, SCL) vs. VDD and
FIGURE 2-63: VOL (SDA) vs. VDD and Temperature (IOL = 3 mA).
5.5V
VIL (V)
1.5
2.7V
1 -40 0 40 Temperature (C) 80 120
FIGURE 2-62: Temperature.
VIL (SDA, SCL) vs. VDD and
(c) 2008 Microchip Technology Inc.
DS22096A-page 33
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
1.2 1 0.8 VDD (V) 0.6 0.4 0.2 0 -40 0 40 Temperature (C) 80 120
2.7V 5.5V
2.1
Test Circuits
+5V VIN Offset GND A W B + VOUT
2.5V DC
FIGURE 2-64: and Temperature.
POR/BOR Trip point vs. VDD
FIGURE 2-65: Test.
-3 db Gain vs. Frequency
DS22096A-page 34
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP453X/455X/463X/465X
Pin Weak Pull-up/ down (1)
Single Rheo Pot (1) Rheo 8L 1 2 3 4 -- -- -- -- 5 6 -- -- 7 8 9 Legend: 8L 1 2 3 4 -- -- -- 5 6 7 -- -- -- 8 9 10L 1 2 3 4 5 6 -- -- 7 8 -- -- 9 10 11
Dual Pot 14L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- 16L 16 1 2 3, 4 5 6 7 8 9 10 11, 12 13 14 15 17 HVC/A0 SCL SDA VSS P1B P1W P1A P0A P0W P0B NC A2 A1 VDD EP I I I/O -- A A A A A A -- I I -- -- HV w/ST HV w/ST HV w/ST P Analog Analog Analog Analog Analog Analog -- HV w/ST HV w/ST P -- Symbol I/O Buffer Type
Standard Function
"smart" No No -- No No No No No No -- "smart" "smart" -- --
High Voltage Command / Address 0. I2C clock input. I2C serial data I/O. Open Drain output Ground Potentiometer 1 Terminal B Potentiometer 1 Wiper Terminal Potentiometer 1 Terminal A Potentiometer 0 Terminal A Potentiometer 0 Wiper Terminal Potentiometer 0 Terminal B No Connection Address 2 Address 1 Positive Power Supply Input Exposed Pad (Note 2)
HV w/ST = High Voltage tolerant input (with Schmidtt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power The pin's "smart" pull-up shuts off while the pin is forced low. This is done to reduce the standby and shutdown current. The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device's VSS pin.
Note 1: 2:
(c) 2008 Microchip Technology Inc.
DS22096A-page 35
MCP453X/455X/463X/465X
3.1 High Voltage Command / Address 0 (HVC/A0) 3.7 Potentiometer Terminal A
The terminal A pin is available on the MCP4XX1 devices, and is connected to the internal potentiometer's terminal A. The potentiometer's terminal A is the fixed connection to the Full-Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP4XX2 devices, and the internally terminal A signal is floating. MCP46X1 devices have two terminal A pins, one for each resistor network.
The HVC/A0 pin is the Address 0 input for the I2C interface as well as the High Voltage Command pin. At the device's POR/BOR the value of the A0 address bit is latched. This input along with the A2 and A1 pins completes the device address. This allows up to 8 MCP45xx/46xx devices can be on a single I2C bus. During normal operation the the voltage on this pin determines if the I2C command is a normal command or a High Voltage command (when HVC/A0 = VIHH).
3.2
Serial Clock (SCL)
The SCL pin is the serial interfaces Serial Clock pin. This pin is connected to the Host Controllers SCL pin. The MCP45XX/46XX is a slave device, so it's SCL pin accepts only external clock signals.
3.3
Serial Data (SDA)
3.8
Address 2 (A2)
The SDA pin is the serial interfaces Serial Data pin. This pin is connected to the Host Controllers SDA pin. The SDA pin is an open-drain N-channel driver.
The A2 pin is the I2C interface's Address 2 pin. Along with the A1 and A0 pins, up to 8 MCP45XX/46XX devices can be on a single I2C bus.
3.4
Ground (VSS)
3.9
Address 1 (A1)
The VSS pin is the device ground reference.
The A2 pin is the I2C interface's Address 1 pin. Along with the A2 and A0 pins, up to 8 MCP45XX/46XX devices can be on a single I2C bus.
3.5
Potentiometer Terminal B 3.10 Positive Power Supply Input (VDD)
The VDD pin is the device's positive power supply input. The input power supply is relative to VSS. While the device VDD < Vmin (2.7V), the electrical performance of the device may not meet the data sheet specifications.
The terminal B pin is connected to the internal potentiometer's terminal B. The potentiometer's terminal B is the fixed connection to the Zero Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. MCP46XX devices have two terminal B pins, one for each resistor network.
3.11
No Connect (NC)
These pins should be either connected to VDD or VSS.
3.12
Exposed Pad (EP)
3.6
Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal potentiometer's terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. MCP46XX devices have two terminal W pins, one for each resistor network.
This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink.
DS22096A-page 36
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
4.0 FUNCTIONAL OVERVIEW
4.1.2 BROWN-OUT RESET
This Data Sheet covers a family of thirty-two Digital Potentiometer and Rheostat devices that will be referred to as MCP4XXX. The MCP4XX1 devices are the Potentiometer configuration, while the MCP4XX2 devices are the Rheostat configuration. As the Device Block Diagram shows, there are four main functional blocks. These are: * * * * POR/BOR Operation Memory Map Resistor Network Serial Interface (I2C) When the device powers down, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage decreases below the VPOR/VBOR voltage the Serial Interface is disabled. If the VDD voltage decreases below the VRAM voltage the following happens: * Volatile wiper registers may become corrupted * TCON register may become corrupted As the voltage recovers above the VPOR/VBOR voltage see Section 4.1.1 "Power-on Reset". Serial commands not completed due to a brown-out condition may cause the volatile memory location to become corrupted.
The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and I2C operation are described in their own sections. The Device Commands commands are discussed in Section 7.0 "Device Commands".
4.2
Memory Map
4.1
POR/BOR Operation
The device memory map supports 16 locations, of which 3 locations are used. Each location is 9-bits wide (16x9 bits). This memory space is shown in Table 4-1.
The Power-on Reset is the case where the device is having power applied to it starting from the VSS level. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. The devices RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less than 1.8V. When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In this region, the device is capable of incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed.
TABLE 4-1:
Address 00h 01h 02h 03h 04h 05h
MEMORY MAP
Function Memory Type RAM RAM -- -- RAM RAM --
Volatile Wiper 0 Volatile Wiper 1 Reserved Reserved Volatile TCON Register Reserved
06h - 0Fh Reserved
4.1.1
POWER-ON RESET
4.2.1
VOLATILE MEMORY (RAM)
When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage the following happens: * Volatile wiper register is loaded with value in the corresponding non-volatile wiper register * The TCON register is loaded it's default value * The device is capable of digital operation
There are four Volatile Memory locations. These are: * Volatile Wiper 0 * Volatile Wiper 1 (Dual Resistor Network devices only) * Terminal Control (TCON) Register * Reserved The volatile memory starts functioning at the RAM retention voltage (VRAM).
4.2.1.1
Address 05h (Reserved)
This memory location is Reserved and is mapped to the Status Register of the Non-Volatile MCP45XX/ 46XX devices. Since the Non-Volatile devices bits are not used by the volatile device, this location is reserved. Reading this address wil result in a value of 1F7h.
(c) 2008 Microchip Technology Inc.
DS22096A-page 37
MCP453X/455X/463X/465X
4.2.1.2 Terminal Control (TCON) Register
This register contains 8 control bits. Four bits are for Wiper 0, and four bits are for Wiper 1. Register 4-1 describes each bit of the TCON register. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. The value that is written to this register will appear on the resistor network terminals when the serial command has completed. When the WL1 bit is enabled, writes to the TCON register bits R1HW, R1A, R1W, and R1B are inhibited. When the WL0 bit is enabled, writes to the TCON register bits R0HW, R0A, R0W, and R0B are inhibited. On a POR/BOR this register is loaded with 1FFh (9-bits), for all terminals connected. The Host Controller needs to detect the POR/BOR event and then update the Volatile TCON register value. Additionally, there is a bit which enables the operation of General Call commands.
DS22096A-page 38
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
REGISTER 4-1:
R/W-1 GCEN bit 8 Legend: R = Readable bit -n = Value at POR bit 8 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TCON BITS (ADDRESS = 0x04) (1)
R/W-1 R1A R/W-1 R1W R/W-1 R1B R/W-1 R0HW R/W-1 R0A R/W-1 R0W R/W-1 R0B bit 0
R/W-1 R1HW
GCEN: General Call Enable bit This bit specifies if I2C General Call commands are accepted 1 = Enable Device to "Accept" the General Call Address (0000h) 0 = The General Call Address is disabled R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the "shutdown" configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 1 is forced to the hardware pin "shutdown" configuration R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the "shutdown" configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 0 is forced to the hardware pin "shutdown" configuration R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network These bits do not affect the wiper register values.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
(c) 2008 Microchip Technology Inc.
DS22096A-page 39
MCP453X/455X/463X/465X
NOTES:
DS22096A-page 40
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
5.0 RESISTOR NETWORK
5.1 Resistor Ladder Module
The Resistor Network has either 7-bit or 8-bit resolution. Each Resistor Network allows zero scale to full-scale connections. Figure 5-1 shows a block diagram for the resistive network of a device. The Resistor Network is made up of several parts. These include: * Resistor Ladder * Wiper * Shutdown (Terminal Connections) Devices have either one or two resistor networks, These are referred to as Pot 0 and Pot 1. The resistor ladder is a series of equal value resistors (RS) with a connection point (tap) between the two resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see Figure 5-1). The end points of the resistor ladder are connected to analog switches which are connected to the device Terminal A and Terminal B pins. The RAB (and RS) resistance has small variations over voltage and temperature. For an 8-bit device, there are 256 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and terminal B). For a 7-bit device, there are 128 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal A and terminal B). Equation 5-1 shows the calculation for the step resistance.
A
8-Bit N= 257 (1) (100h) 256 (FFh) 255 (FEh) 7-Bit N= 128 (80h) 127 (7Fh) 126 (7Eh)
RS
RW
RS
RW (1)
(1)
EQUATION 5-1:
R AB R S = ------------( 256 )
RS CALCULATION
8-bit Device
R RAB S
RW
W
RW 1 (1) (01h) 0 (00h) 1 (01h) 0 (00h) R AB R S = ------------( 128 ) 7-bit Device
RS
RW
(1)
Analog Mux
B
Note 1: The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B, and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This RW variation has greater effects on some specifications (such as INL) for the smaller resistance devices (5.0 k) compared to larger resistance devices (100.0 k).
FIGURE 5-1:
Resistor Block Diagram.
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5.2 Wiper
TABLE 5-1:
Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) pin. A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The wiper can connect directly to Terminal B or to Terminal A. A zero-scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full-scale connections, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h). In these configurations the only resistance between the Terminal W and the other Terminal (A or B) is that of the analog switches. A wiper setting value greater than full-scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a Full-Scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map. Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B.
VOLATILE WIPER VALUE VS. WIPER POSITION MAP
Properties
Wiper Setting 7-bit Pot 8-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h Reserved (Full-Scale (W = A)), Increment and Decrement commands ignored Full-Scale (W = A), Increment commands ignored W=N W = N (Mid-Scale) W=N Zero Scale (W = B) Decrement command ignored
EQUATION 5-2:
RWB CALCULATION
8-bit Device
R AB N R WB = ------------- + R W ( 256 ) N = 0 to 256 (decimal) R AB N R WB = ------------- + R W ( 128 ) N = 0 to 128 (decimal)
7-bit Device
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5.3 Shutdown
5.3.2
Shutdown is used to minimize the device's current consumption. The MCP4XXX achieves this through the Terminal Control Register (TCON).
INTERACTION OF RxHW BIT AND RxA, RxW, AND RxB BITS (TCON REGISTER)
Using the TCON bits allows each resistor network (Pot 0 and Pot 1) to be individually "shutdown". The state of the RxHW bit does NOT corrupt the other bit values in the TCON register nor the value of the Volatile Wiper Registers. When the Shutdown mode is exited (RxHW changes state from "0" to "1"): * The device returns to the Wiper setting specified by the Volatile Wiper value * The RxA, RxB, and RxW bits return to controlling the terminal connection state of that resistor network
5.3.1
TERMINAL CONTROL REGISTER (TCON)
The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B, and W) to the Resistor Network. This bits are described in Register 4-1. When the RxHW bit is a "0", the selected resistor network is forced into the following state: * The PxA terminal is disconnected * The PxW terminal is simultaneously connected to the PxB terminal (see Figure 5-2) * The Serial Interface is NOT disabled, and all Serial Interface activity is executed Alternate low power configurations may be achieved with the RxA, RxW, and RxB bits. Note 1: The RxHW bits are identical to the RxHW bits of the MCP41XX/42XX devices. The MCP42XX devices also have a SHDN pin which forces the resistor network into the same state as that resistor networks RxHW bit. 2: When RxHW = "0", the state of the TCON register RxA, RxW, and RxB bits is overridden (ignored). When the state of the RxHW bit returns to "1", the TCON register RxA, RxW, and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW, and RxB bits.
A Resistor Network W
B
FIGURE 5-2: Configuration.
Resistor Network Shutdown
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6.0 SERIAL INTERFACE (I2C)
6.1 Signal Descriptions
The MCP45XX/46XX devices support the I2C serial protocol. The MCP45XX/46XX I2C's module operates in Slave mode (does not generate the serial clock). Figure 6-1 shows a typical I2C Interface connection. All I2C interface signals are high-voltage tolerant. The MCP45XX/46XX devices use the two-wire I2C serial interface. This interface can operate in standard, fast or High-Speed mode. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions. The MCP45XX/46XX device works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Communication is initiated by the master (microcontroller) which sends the START bit, followed by the slave address byte. The first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the R/W bit. Refer to the Phillips I the I2C specifications.
2C
The I2C interface uses up to five pins (signals). These are: * * * * * SDA (Serial Data) SCL (Serial Clock) A0 (Address 0 bit) A1 (Address 1 bit) A2 (Address 2 bit)
6.1.1
SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the device. The value on this pin is latched on the rising edge of the SCL signal when the signal is an input. With the exception of the START and STOP conditions, the high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. During the high period of the clock the SDA pin's value (high or low) must be stable. Changes in the SDA pin's value while the SCL pin is HIGH will be interpreted as a START or a STOP condition.
6.1.2
SERIAL CLOCK (SCL)
document for more details of
Typical I2C Interface Connections Host Controller SCL SDA I/O
(1)
The Serial Clock (SCL) signal is the clock signal of the device. The rising edge of the SCL signal latches the value on the SDA pin. The MCP45XX/46XX supports three I2C interface clock modes: * Standard Mode: clock rates up to 100 kHz * Fast Mode: clock rates up to 400 kHz * High-Speed Mode (HS mode): clock rates up to 3.4 MHz The MCP4XXX will not strech the clock signal (SCL) since memory read acceses occur fast enough. Depending on the clock rate mode, the interface will display different characteristics.
MCP4XXX SCL SDA HVC/A0 A1 (2, 3) A2 (2, 3)
(2)
6.1.3
THE ADDRESS BITS (A2:A1:A0)
Note 1: If High voltage commands are desired, some type of external circuitry needs to be implemented. 2: These pins have internal pull-ups. If faster rise times are required, then external pull-ups should be added. 3: This pin could be tied high, low, or connected to an I/O pin of the Host Controller.
There are up to three hardware pins used to specify the device address. The number of adress pins is determined by the part number. Address 0 is multiplexed with the High Voltage Command (HVC) function. So the state of A0 is latched on the MCP4XXX's POR/BOR event. The state of the A2 and A1 pins should be static, that is they should be tied high or tied low.
6.1.3.1
FIGURE 6-1: Diagram.
Typical I2C Interface Block
The High Voltage Command (HVC) Signal
The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands are supported for compatibility with the non-volatile devices. The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal.
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6.2 I2C Operation
6.2.1.3 Acknowledge (A) Bit
The MCP45XX/46XX's I2C module is compatible with the Philips I2C specification. The following lists some of the modules features: * 7-bit slave addressing * Supports three clock rate modes: - Standard mode, clock rates up to 100 kHz - Fast mode, clock rates up to 400 kHz - High-speed mode (HS mode), clock rates up to 3.4 MHz * Support Multi-Master Applications * General call addressing * Internal weak pull-ups on interface signals The I2C 10-bit addressing mode is not supported. The Philips I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP4XXX is defined in Section 7.0. The A bit (see Figure 6-4) is typically a response from the receiving device to the transmitting device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave device will supply an A response after the Start bit and 8 "data" bits have been received. an A bit has the SDA signal low.
SDA SCL
D0 8
A 9
FIGURE 6-4:
Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal high. Table 6-1 shows some of the conditions where the Slave Device will issue a Not A (A). If an error condition occurs (such as an A instead of A), then an START bit must be issued to reset the command state machine.
6.2.1
I2C BIT STATES AND SEQUENCE
Figure 6-8 shows the I2C transfer sequence. The serial clock is generated by the master. The following definitions are used for the bit states: * Start bit (S) * Data bit * Acknowledge (A) bit (driven low) / No Acknowledge (A) bit (not driven low) * Repeated Start bit (Sr) * Stop bit (P)
TABLE 6-1:
MCP45XX/MCP46XX A / A RESPONSES
Acknowledge Bit Response A A A A After device has received address and command Comment Only if GCEN bit is set
Event General Call Slave Address valid Slave Address not valid Device Memory Address and specified command (AD3:AD0 and C1:C0) are an invalid combination Bus Collision
6.2.1.1
Start Bit
The Start bit (see Figure 6-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is "High".
SDA SCL S
1st Bit
2nd Bit
FIGURE 6-2: 6.2.1.2 Data Bit
Start Bit.
The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 6-5).
N.A.
SDA SCL
1st Bit
2nd Bit
I2C Module Resets, or a "Don't Care" if the collision occurs on the Masters "Start bit".
Data Bit
FIGURE 6-3:
Data Bit.
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6.2.1.4 Repeated Start Bit 6.2.1.5 Stop Bit
The Repeated Start bit (see Figure 6-5) indicates the current Master Device wishes to continue communicating with the current Slave Device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is "High". Note 1: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". The Stop bit (see Figure 6-6) Indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is "High". A Stop bit resets the I2C interface of all MCP4XXX devices.
SDA A / A SCL P
FIGURE 6-6: Transmit Mode. 6.2.2
Stop Condition Receive or
CLOCK STRETCHING
"Clock Stretching" is something that the receiving Device can do, to allow additional time to "respond" to the "data" that has been received. The MCP4XXX will not strech the clock signal (SCL) since memory read acceses occur fast enough.
SDA
1st Bit
6.2.3
ABORTING A TRANSMISSION
SCL Sr = Repeated Start
If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they corrupt the device.
FIGURE 6-5: Waveform.
Repeat Start Condition
SDA SCL S 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A/A P
FIGURE 6-7:
SDA
Typical 8-Bit I2C Waveform Format.
SCL START Condition Data allowed to change Data or A valid STOP Condition
FIGURE 6-8:
I2C Data States and Bit Sequence.
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6.2.4 ADDRESSING
Slave Address S A6 A5 A4 A3 A2 A1 A0 R/W "0" "1" "0" "1" See Table 6-2 Start bit R/W bit R/W = 0 = write R/W = 1 = read A/A The address byte is the first byte received following the START condition from the master device. The address contains four (or more) fixed bits and (up to) three user defined hardware address bits (pins A2, A1, and A0). These 7-bits address the desired I2C device. The A7:A4 address bits are fixed to "0101" and the device appends the value of following three address pins (A2, A1, A0). Address pins that are not present on the device are pulled up (a bit value of `1'). Since there are up to three adress bits controlled by hardware pins, there may be up to eight MCP4XXX devices on the same I2C bus. Figure 6-9 shows the slave address byte format, which contains the seven address bits. There is also a read/ write bit. Table 6-2 shows the fixed address for device.
A bit (controlled by slave device) A = 0 = Slave Device Acknowledges byte A = 1 = Slave Device does not Acknowledge byte
FIGURE 6-9: I2C Control Byte. TABLE 6-2:
Slave Address Bits in the
DEVICE SLAVE ADDRESSES
2 4 8 4
Hardware Address Pins
The hardware address bits (A2, A1, and A0) correspond to the logic level on the associated address pins. This allows up to eight devices on the bus. These pins have a weak pull-up enabled when the VDD < VBOR. The weak pull-up utilizes the "smart" pull-up technology and exhibits the same characteristics as the High-voltage tolerant I/O structure. The state of the A0 address pin is latch on POR/BOR. This is required since High Voltage commands force this pin (HVC/A0) to the VIHH level.
Comment Supports up to devices. Note 1 MCP45X2 `0101 1'b + A1:A0 Supports up to devices. Note 1 MCP46X1 `0101'b + A2:A1:A0 Supports up to devices. Note 1 MCP46X2 `0101 1'b + A1:A0 Supports up to devices. Note 1 Note 1: A0 is used for High-Voltage commands and the value is latched at POR.
Device Address MCP45X1 `0101 11'b + A0
6.2.5
SLOPE CONTROL
The MCP45XX/46XX implements slope control on the SDA output. As the device transitions from HS mode to FS mode, the slope control parmameter will change from the HS specification to the FS specification. For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmidt trigger at SDA and SCL inputs.
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6.2.6
2
HS MODE
The I C specification requires that a high-speed mode device must be `activated' to operate in high-speed (3.4 Mbit/s) mode. This is done by the Master sending a special address byte following the START bit. This byte is referred to as the high-speed Master Mode Code (HSMMC). The MCP45XX/46XX device does not acknowledge this byte. However, upon receiving this command, the device switches to HS mode. The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next STOP condition. The master code is sent as follows: 1. 2. START condition (S) High-Speed Master Mode Code (0000 1XXX), The XXX bits are unique to the high-speed (HS) mode Master. No Acknowledge (A)
After switching to the High-Speed mode, the next transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. The Master Device can then either issue a Repeated Start bit to address a different device (at High-Speed) or a Stop bit to return to Fast/Standard bus speed. After the Stop bit, any other Master Device (in a Multi-Master system) can arbitrate for the I2C bus. See Figure 6-10 for illustration of HS mode command sequence. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification.
6.2.6.1
Slope Control
The slope control on the SDA output is different between the Fast/Standard Speed and the High-Speed clock modes of the interface.
3.
6.2.6.2
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10 ns during HS mode. F/S-mode HS-mode
P F/S-mode "Data" A/A
S `0 0 0 0 1 X X X'b
A Sr `Slave Address' R/W A
HS-mode continues Sr `Slave Address' R/W A Control Byte
HS Select Byte
Control Byte
Command/Data Byte(s)
S = Start bit Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS Mode)
FIGURE 6-10:
HS Mode Sequence.
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6.2.7 GENERAL CALL TABLE 6-3:
7-bit Command
(1, 2, 3)
GENERAL CALL COMMANDS
Comment
The General Call is a method that the "Master" device can communicate with all other "Slave" devices. In a Multi-Master application, the other Master devices are operating in Slave mode. The General Call address has two documented formats. These are shown in Figure 6-11. We have added a MCP45XX/46XX format in this figure as well. This will allow customers to have multiple I2C Digital Potentiometers on the bus and have them operate in a synchronous fashion (analogous to the DAC Sync pin functionality). If these MCP45XX/46XX 7-bit commands conflict with other I2C devices on the bus, then the customer will need two I2C busses and ensure that the devices are on the correct bus for their desired application functionality. Dual Pot devices can not update both Pot0 and Pot1 from a single command. To address this, there are General Call commands for the Wiper 0, Wiper 1, and the TCON registers. Table 6-3 shows the General Call Commands. Three commands are specified by the I2C specification and are not applicable to the MCP45XX/46XX (so command is Not Acknowledged) The MCP45XX/46XX General Call Commands are Acknowledge. Any other command is Not Acknowledged. Note: Only one General Call command per issue of the General Call control byte. Any additional General Call commands are ignored and Not Acknowledged.
`1000 00d'b Write Next Byte (Third Byte) to Volatile Wiper 0 Register `1001 00d'b Write Next Byte (Third Byte) to Volatile Wiper 1 Register `1100 00d'b Write Next Byte (Third Byte) to TCON Register `1000 010'b Increment Wiper 0 Register or `1000 011'b `1001 010'b Increment Wiper 1 Register or `1001 011'b `1000 100'b Decrement Wiper 0 Register or `1000 101'b `1001 100'b Decrement Wiper 1 Register or `1001 101'b Note 1: Any other code is Not Acknowledged. These codes may be used by other devices on the I2C bus. The 7-bit command always appends a "0" to form 8-bits. . "d" is the D8 bit for the 9-bit write value.
2: 3:
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Second Byte S0 000 0 000AXXXXX "7-bit Command" XX0AP
General Call Address
Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000) `0000 011'b - Reset and write programmable part of slave address by hardware. `0000 010'b - Write programmable part of slave address by hardware. `0000 000'b - NOT Allowed MCP45XX/MCP46XX 7-bit Commands `1000 01x'b - Increment Wiper 0 Register. `1001 01x'b - Increment Wiper 1 Register. `1000 10x'b - Decrement Wiper 0 Register. `1001 10x'b - Decrement Wiper 1 Register.
The Following is a Microchip Extension to this General Call Format Second Byte S000 0 0000 AXXXXX "7-bit Command" Xd 0 Ad d
Third Byte d d d d d d AP
General Call Address
"0" for General Call Command
MCP45XX/MCP46XX 7-bit Commands `1000 00d'b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register. `1001 00d'b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register. `1100 00d'b - Write Next Byte (Third Byte) to TCON Register.
The Following is a "Hardware General Call" Format Second Byte S00 00 000 0AXXXXX "7-bit Command" XX1
n occurrences of (Data + A) AX X X X X X X X A P
General Call Address
This indicates a "Hardware General Call" MCP45XX/MCP46XX will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered.
FIGURE 6-11:
General Call Formats.
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7.0 DEVICE COMMANDS
7.1 Command Byte
The MCP4XXX's I2C command formats are specified in this section. The I2C protocol does not specify how commands are formatted. The MCP4XXX supports four basic commands. Depending on the location accessed determines the commands that are supported. For the Volatile Wiper Registers, these commands are: * * * * Write Data Read Data Increment Data Decrement Data The MCP4XXX's Command Byte has three fields: the Address, the Command Operation, and 2 Data bits, see Figure 7-1. Currently only one of the data bits is defined (D8). The device memory is accessed when the Master sends a proper Command Byte to select the desired operation. The memory location getting accessed is contained in the Command Byte's AD3:AD0 bits. The action desired is contained in the Command Byte's C1:C0 bits, see Table 7-1. C1:C0 determines if the desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers. If the Address bits and Command bits are not a valid combination, then the MCP4XXX will generate a Not Acknowledge pulse to indicate the invalid combination. The I2C Master device must then force a Start Condition to reset the MCP4XXX's 2C module. D9 and D8 are the most significant bits for the digital potentiometer's wiper setting. The 8-bit devices utilize D8 as their MSb while the 7-bit devices utilize D7 (from the data byte) as it's MSb. COMMAND BYTE AAAAACCDDA DDDD1098 3210 MSbits (Data) MCP4XXX Memory Address Command Operation bits 00 = Write Data 01 = Increment 10 = Decrement 11 = Read Data
For the TCON Register, these commands are: * Write Data * Read Data These commands have formats for both a single command or continuous commands. These commands are shown in Table 7-1. Each command has two operational states. These operational states are referred to as: * Normal Serial Commands * High-Voltage Serial Commands Note: High Voltage commands are supported for compatibility with Non-Volatile devices in the family.
TABLE 7-1:
I2C COMMANDS
Operates on Volatile/ # of Bit Clocks (1) Non-Volatile memory
Command Operation Write Data Mode
Single 29 Both Continuous 18n + 11 Volatile Only Read Data Single 29 Both Random 48 Both Continuous 18n + 11 Both Increment Single 20 Volatile Only Continuous 9n + 11 Volatile Only Decrement Single 20 Volatile Only Continuous 9n + 11 Volatile Only Note 1: "n" indicates the number of times the command operation is to be repeated. Normal serial commands are those where the HVC pin is driven to VIH or VIL. With High-Voltage Serial Commands, the HVC pin is driven to VIHH. In each mode, there are four possible commands. Table 7-2 shows the supported commands for each memory location. Table 7-3 shows an overview of all the device commands and their interaction with other device features.
FIGURE 7-1:
Command Byte Format.
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TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS
Address Command Operation Value 00h Function Volatile Wiper 0 Write Data Read Data (3) Increment Wiper Decrement Wiper 01h Volatile Wiper 1 Write Data Read Data (3) Increment Wiper Decrement Wiper 02h 03h 04h
(2)
Data (10-bits) (1) nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn -- -- -- -- nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn
Comment
Reserved Reserved
-- -- Read Data (3)
Volatile TCON Register Write Data Reserved Read Data (3)
05h (2)
Maps to Non-Volitile MCP45XX/46XX device's STATUS Register
06h - 0Fh (2) Reserved
Note 1: 2: 3:
--
--
The Data Memory is only 9-bits wide, so the MSb is ignored by the device. Increment or Decrement commands are invalid for these addresses. I2C read operation will read 2 bytes, of which the 10-bits of data are contained within.
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7.2 Data Byte 7.3 Error Condition
Only the Read Command and the Write Command have Data Byte(s). The Write command concatenates the 8-bits of the Data Byte with the one data bit (D8) contained in the Command Byte to form 9-bits of data (D8:D0). The Command Byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to Full-Scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B. The D9 bit is currently unused. If the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination, the MCP4XXX will Acknowledge the I2C bus. If the address bits and command bits are an invalid combination, then the MCP4XXX will Not Acknowledge the I2C bus. Once an error condition has occurred, any following commands are ignored until the I2C bus is reset with a Start Condition.
7.3.1
ABORTING A TRANSMISSION
A Restart or Stop condition in the expected data bit position will abort the current command sequence and
TABLE 7-3:
COMMANDS
Command Name # of Bits High Voltage (VIHH) on HVC pin? -- -- -- -- Yes Yes Yes Yes
Write Data Read Data Increment Wiper Decrement Wiper High Voltage Write Data High Voltage Read Data High Voltage Increment Wiper High Voltage Decrement Wiper
29 29 20 20 29 29 20 20
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7.4 Write Data Normal and High Voltage
7.4.2 CONTINUOUS WRITES TO VOLATILE MEMORY
A continuous write mode of operation is possible when writing to the volatile memory registers (address 00h, 01h, and 04h). This continuous write mode allows writes without a Stop or Restart condition or repeated transmissions of the I2C Control Byte. Figure 7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. The sequence ends with the master sending a STOP or RESTART condition.
The Write Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command, see Figure 7-2, includes the I2C Control Byte, an A bit, the MCP4XXX Command Byte, an A bit, the MCP4XXX Data Byte, an A bit, and a Stop (or Restart) condition. The MCP4XXX generates the A / A bits. A Write command to a Volatile memory location changes that location after a properly formatted Write Command and the A / A clock have been received.
7.4.3
7.4.1
SINGLE WRITE TO VOLATILE MEMORY
THE HIGH VOLTAGE COMMAND (HVC) SIGNAL
For volatile memory locations, data is written to the MCP4XXX after every byte transfer (during the Acknowledge). If a Stop or Restart condition is generated during a data transfer (before the A), the data will not be written to the MCP4XXX. After the A bit, the master can initiate the next sequence with a Stop or Restart condition. Refer to Figure 7-2 for the byte write sequence.
The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage operational state. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal.
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Write bit Fixed Address S010 Variable Address 1 A2 A1 A0 0 A Device Memory Address
Command
Write "Data" bits
AD AD AD AD 32100
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Write Data bits
Control Byte
WRITE Command
FIGURE 7-2:
I2C Write Sequence.
Write bit Device Memory Address
Fixed Address S01
Variable Address
Command
Write "Data" bits
0 1 A2 A1 A0 0 A Control Byte
AD AD AD AD 32100
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A Write Data bits
WRITE Command
AD AD AD AD 32100
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A Write Data bits STOP bit
WRITE Command
AD AD AD AD 32100
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P Write Data bits
WRITE Command Note:
Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, and 04h) or the TCON register I2C Continuous Volatile Wiper Write.
FIGURE 7-3:
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7.5 Read Data Normal and High Voltage
7.5.1 SINGLE READ
Figure 7-4 show the waveforms for a single read. For single reads the master sends a STOP or RESTART condition after the data byte is sent from the slave.
The Read Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command, see Figure 7-4, includes the Start condition, I2C Control Byte (with R/W bit set to "0"), A bit, MCP4XXX Command Byte, A bit, followed by a Repeated Start bit, I2C Control Byte (with R/W bit set to "1"), and the MCP4XXX transmitting the requested Data High Byte, and A bit, the Data Low Byte, the Master generating the A, and Stop condition. The I2C Control Byte requires the R/W bit equal to a logic one (R/W = 1) to generate a read sequence. The memory location read will be the last address contained in a valid write MCP4XXX Command Byte or address 00h if no write operations have occurred since the device was reset (Power-on Reset or Brown-out Reset). Read operations initially include the same address byte sequence as the write sequence (shown in Figure 6-9). This sequence is followed by another control byte (including the Start condition and Ackowledge) with the R/W bit equal to a logic one (R/W = 1) to indicate a read. The MCP4XXX will then transmit the data contained in the addressed register. This is followed by the master generating an A bit in preparation for more data, or an A bit followed by a Stop. The sequence is ended with the master generating a Stop or Restart condition. The internal address pointer is maintained.
7.5.1.1
Random Read
Figure 7-5 shows the sequence for a Random Reads. Refer to Figure 7-5 for the random byte read sequence.
7.5.2
CONTINUOUS READS
Continuous reads allows the devices memory to be read quickly. Continuous reads are possible to all memory locations. If a non-volatile memory write cycle is occurring, then Read commands may only access the volatile memory locations. Figure 7-6 shows the sequence for three continuous reads. For continuous reads, instead of transmitting a Stop or Restart condition after the data transfer, the master reads the next data byte. The sequence ends with the master Not Acknowledging and then sending a Stop or Restart.
7.5.3
THE HIGH VOLTAGE COMMAND (HVC) SIGNAL
The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP4XXXs internal VDD signal. 7.5.4 IGNORING AN I2C TRANSMISSION AND "FALLING OFF" THE BUS
The MCP4XXX expects to receive entire, valid I2C commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the SDA signal. All signals will be ignored until the next valid Start condition and Control Byte are received.
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Read bit Fixed Address S010 Variable Address 1 A2 A1 A0 1 A 0 0 0 000 STOP bit Read Data bits 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 Read bits P
Control Byte
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP45xx/46xx retains the last "Device Memory Address" that it has received. This is the MCP45XX/46XX does not "corrupt" the "Device Memory Address" after Repeated Start or Stop conditions. 4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
FIGURE 7-4:
I2C Read (Last Memory Address Accessed).
Write bit Fixed Address Variable Address A Device Memory Address Repeated Start bit
Command 1 x X A Sr
S0
1 0 1 A2 A1 A0 0 Control Byte
AD AD AD AD 32101
READ Command STOP bit Read bit Read Data bits 0 0 000 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 Read bits P
01
0 1 A2 A1 A0 1 Control Byte
A0
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP45XX/46XX retains the last "Device Memory Address" that it has received. This is the MCP45XX/46XX does not "corrupt" the "Device Memory Address" after Repeated Start or Stop conditions.
FIGURE 7-5:
I2C Random Read.
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Read bit Fixed Address S010 Variable Address 1 A2 A1 A0 1 A 0 0 0 000
Read Data bits 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1 Read bits Read Data bits
Control Byte
0
0
0
000
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1
STOP bit Read Data bits 0 0 0 000 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition.
FIGURE 7-6:
I2C Continuos Reads.
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7.6 Increment Wiper Normal and High Voltage
TABLE 7-4:
Current Wiper Setting 7-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 8-bit Pot 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h
INCREMENT OPERATION VS. VOLATILE WIPER VALUE
Wiper (W) Properties Increment Command Operates?
The Increment Command provide a quick and easy method to modify the potentiometer's wiper by +1 with minimal overhead. The Increment Command will only function on the volatile wiper setting memory locations 00h and 01h. Note: Table 7-2 shows the valid addresses for the Increment Wiper command. Other addresses are invalid.
Reserved No (Full-Scale (W = A)) Full-Scale (W = A) W=N W = N (Mid-Scale) W=N Zero Scale (W = B) Yes Yes No
When executing an Increment Command, the volatile wiper setting will be altered from n to n+1 for each Increment Command received. The value will increment up to 100h max on 8-bit devices and 80h on 7-bit devices. If multiple Increment Commands are received after the value has reached 100h (or 80h), the value will not be incremented further. Table 7-4 shows the Increment Command versus the current volatile wiper value. Refer to Figure 7-7 for the Increment Command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, The Increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. Note: The command sequence can go from an increment to any other valid command for the specified address.
7.6.1
THE HIGH VOLTAGE COMMAND (HVC) SIGNAL
The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. Signals > VIHH (~8.5V) on the HVC/A0 pin puts MCP45XX/46XX devices into High Voltage mode. Note: There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin.
The advantage of using an Increment Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. Write bit Fixed Address S0 Variable Address A Device Memory Address
The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal.
Command 1x AD AD AD AD XA43210 1x X A P (2)
1 0 1 A2 A1 A0 0 Control Byte
AD AD AD AD 32100
INCR Command (n+1)
INCR Command (n+2)
Note 1: Increment Command (INCR) only functions when accessing the volatile wiper reg-
isters (AD3:AD0 = 0h and 1h).
2: This command sequence does not need to terminate (using the Stop bit) and can
change to any other desired command sequence (Increment, Read, or Write). FIGURE 7-7: I2C Increment Command Sequence.
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7.7 Decrement Wiper Normal and High Voltage
TABLE 7-5:
Current Wiper Setting 7-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 8-bit Pot 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h
DECREMENT OPERATION VS. VOLATILE WIPER VALUE
Wiper (W) Properties Decrement Command Operates?
The Decrement Command provide a quick and easy method to modify the potentiometer's wiper by -1 with minimal overhead. The Decrement Command will only function on the volatile wiper setting memory locations 00h and 01h. Note: Table 7-2 shows the valid addresses for the Decrement Wiper command. Other addresses are invalid.
Reserved No (Full-Scale (W = A)) Full-Scale (W = A) W=N W = N (Mid-Scale) W=N Zero Scale (W = B) No Yes Yes
When executing a Decrement Command, the volatile wiper setting will be altered from n to n-1 for each Decrement Command received. The value will decrement down to 000h min. If multiple Decrement Commands are received after the value has reached 000h, the value will not be decremented further. Table 7-5 shows the Increment Command versus the current volatile wiper value. Refer to Figure 7-8 for the Decrement Command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, The Increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. Note: The command sequence can go from an increment to any other valid command for the specified address.
7.7.1
THE HIGH VOLTAGE COMMAND (HVC) SIGNAL
The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. Signals > VIHH (~8.5V) on the HVC/A0 pin puts MCP45XX/46XX devices into High Voltage mode. Note: There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin.
The advantage of using an Decrement Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. Write bit
The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal.
Fixed Address
S0
Variable Address
Device Memory Address Command
AD AD AD AD 32101 AD AD AD AD 0XXA4321 1 0 X X A P (2)
1 0 1 A2 A1 A0 0 A Control Byte
DECR Command (n-1)
DECR Command (n-2)
Note 1: Decrement Command (DECR) only functions when accessing the volatile wiper
registers (AD3:AD0 = 0h and 1h).
2: This command sequence does not need to terminate (using the Stop bit) and can
change to any other desired command sequence (INCR, Read, or Write). FIGURE 7-8: I2C Decrement Command Sequence.
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8.0 APPLICATIONS EXAMPLES
Non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP453X/455X/463X/465X devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V). The circuit in Figure 8-2 shows the method used on the MCP402X Non-volatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficient voltage level on the HVC pin to change the stored value of the wiper. The MCP402X Non-volatile Digital Potentiometer Evaluation Board User's Guide (DS51546) contains a complete schematic. GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock. For the serial commands, configure the GP2 pin as an input (high impedance). The output state of the GP0 pin will determine the voltage on the HVC pin (VIL or VIH). For high-voltage serial commands, force the GP0 output pin to output a high level (VOH) and configure the GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the HVC pin (when the system voltage is approximately 5V). PIC10F206 GP0 MCP4XXX PIC MCU IO1 R1 IO2 TC1240A C+ VIN CSHDN VOUT MCP45XX HVC MCP46XX C2 C1 GP2 C1 HVC C2
8.1
Techniques to force the HVC pin to VIHH
The circuit in Figure 8-1 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the HVC pin is controlled by the PIC(R) microcontrollers (MCUs) IO2 pin. When the SHDN pin is low, the TC1240A is on and the VOUT voltage is 2 * VDD. The resistor R1 allows the HVC pin to go higher than the voltage such that the PIC MCU's IO2 pin "clamps" at approximately VDD.
R1
FIGURE 8-2: MCP4XXX Non-Volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage.
FIGURE 8-1: Using the TC1240A to generate the VIHH voltage.
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8.2 Using Shutdown
S `1' `1' `1' `1' `1' `1' `1' `1' S P Figure 8-3 shows a possible application circuit where the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to the Bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the RBW rheostat value to the Common B. Disconnecting Terminal B modifies the transistor input by the RAW rheostat value to the Common A. The Common A and Common B connections could be connected to VDD and VSS.
Nine bits of `1' Start bit Start bit Stop bit
FIGURE 8-4: Format.
Software Reset Sequence
Common A
The 1st Start bit will cause the device to reset from a state in which it is expecting to receive data from the Master Device. In this mode, the device is monitoring the data bus in Receive mode and can detect the Start bit forces an internal Reset. The nine bits of `1' are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP45XX/46XX is driving an A bit on the I2C bus, or is in output mode (from a Read command) and is driving a data bit of `0' onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP45XX/46XX holding the bus low. By sending out nine `1' bits, it is ensured that the device will see a A bit (the Master Device does not drive the I2C bus low to acknowledge the data sent by the MCP45XX/46XX), which also forces the MCP45XX/46XX to reset. The 2nd Start bit is sent to address the rare possibility of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP45XX/46XX, AND then as the Master Device returns to normal operation and issues a Start condition while the MCP45XX/46XX is issuing an Acknowledge. In this case, if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP45XX/46XX could initiate a write cycle.
Input A
W
To base of Transistor (or Amplifier)
B Input
Common B Balance Bias
FIGURE 8-3: Example Application Circuit using Terminal Disconnects.
Note:
8.3
Note:
Software Reset Sequence
This technique is documented in AN1028.
The potential for this erroneous write ONLY occurs if the Master Device is reset while sending a Write command to the MCP45XX/46XX.
The Stop bit terminates the current I2C bus activity. The MCP45XX/46XX wait to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command.
At times it may become necessary to perform a Software Reset Sequence to ensure the MCP45XX/46XX device is in a correct and known I2C Interface state. This technique only resets the I2C state machine. This is useful if the MCP45XX/46XX device powers up in an incorrect state (due to excessive bus noise, ...), or if the Master Device is reset during communication. Figure 8-4 shows the communication sequence to software reset the device.
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8.4 Using the General Call Command
The use of the General Call Address Increment, Decrement, or Write commands is analogous to the "Load" feature (LDAC pin) on some DACs (such as the MCP4921). This allows all the devices to "Update" the output level "at the same time". For some applications, the ability to update the wiper values "at the same time may be a requirement, since they delay from writing to one wiper value and then the next may cause application issues. A possible example would be a "tuned" circuit that uses several MCP45XX/ 46XX in rheostat configuration. As the system condition changes (temperature, load, ...) these devices need to be changed (incremented/decremented) to adjust for the system change. These changes will either be in the same direction or in opposite directions. With the Potentiometer device the customer can either select the PxB terminals (same direction) or the PxA terminal(s) (opposite direction). Figure 8-6 shows that the update of six devices takes 6*TI2CDLY time in "normal" operation, but only 1*TI2CDLY time in "General Call" operation. Note: The application system may need to partition the I2C bus into multiple busses to ensure that the MCP45XX/46XX General Call commands do not conflict with the General Call commands that the other I2C devices may have defined. Also if only a portion of the MCP45XX/46XX devices are to require this synchronous operation, then the devices that should not receive these commands should be on the second I2C bus. Figure 8-5 shows two I2C bus configurations. In many cases, the single I2C bus configuration will be adequate. For applications that do not want all the MCP45XX/46XX devices to do General Call support or have a conflict with General Call commands, the multiple I2C bus configuration would be used. Single I2C Bus Configuration Device 1 Host Controller Device 2 Device 4 Device 3 Device n
Multiple I2C Bus Configuration Device 1a Host Bus a Controller Device 2a Device 1b Bus b Device 2b Device 1n Bus n Device 2n Device 4n Device 4b Device 3n Device nn Device 4a Device 3b Device nb Device 3a Device na
FIGURE 8-5: Configurations.
Typical Application I2C Bus
Normal Operation INC POT01 TI2CDLY TI2CDLY INC POT02 TI2CDLY INC POT03 TI2CDLY INC POT04 TI2CDLY INC POT05 TI2CDLY INC POT06
General Call Operation INC POTs 01-06 TI2CDLY INC POTs 01-06 INC POTs 01-06 INC POTs 01-06 INC POTs 01-06 INC POTs 01-06
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY = Time from one I2C command completed to completing the next I2C command.
FIGURE 8-6: Updates.
Example Comparison of "Normal Operation" vs. "General Call Operation" wiper
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8.5 Design Considerations
8.5.2 LAYOUT CONSIDERATIONS
In the design of a system with the MCP4XXX devices, the following considerations should be taken into account: * Power Supply Considerations * Layout Considerations Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP4XXX's performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended.
8.5.1
POWER SUPPLY CONSIDERATIONS
The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-7 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD 0.1 F VDD
8.5.3
RESISTOR TEMPCO
Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure 2-12, Figure 2-25, Figure 2-38, and Figure 2-51. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is RAB resistance.
8.5.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins is for compatibility with the non-volatile devices..
0.1 F PIC(R) Microcontroller VSS
A W
MCP453X/455X/ 463X/465X
SCL
B
SDA
VSS
FIGURE 8-7: Connections.
Typical Microcontroller
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9.0 DEVICE OPTIONS
Additional, custom devices are available. These devices have weak pull-up resistors on the SDA and SCL pins. This is useful for applications where the wiper value is programmed durning manufacture and not modified by the system during normal operation. Please contact your local sales office for current information and minimum volumn requirements.
9.1
Custom Options
The custom device will have a "P" (for Pull-up) after the resistance version in the Product Identification System. These device will not be available through Microchip's online Microchip Direct nor Microchip's Sample systems. Example part number: MCP4631-103PE/ST
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NOTES:
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10.0
10.1
DEVELOPMENT SUPPORT
Development Tools
10.2
Technical Documentation
Several development tools are available to assist in your design and evaluation of the MCP45XX/46XX devices. The currently available tools are shown in Table 10-1. These boards may be purchased directly from the Microchip web site at www.microchip.com.
Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 10-2 shows some of these documents.
TABLE 10-1:
Board Name
DEVELOPMENT TOOLS
Part # MCP42XXDM-PTPLS MCP4XXXDM-DB SOIC8EV SOIC14EV Supported Devices MCP42XX MCP42XXX, MCP42XX, MCP46XX, MCP4021, and MCP4011 Any 8-pin device in DIP, SOIC, MSOP, or TSSOP package Any 14-pin device in DIP, SOIC, or MSOP package
MCP42XX PICTail Plus Daughter Board (2) MCP4XXX Digital Potentiometer Daughter Board (1) 8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board 14-pin SOIC/MSOP/DIP Evaluation Board
Note 1: Requires the use of a PICDEM Demo Board (see User's Guide for details) 2: Requires the use of the PIC24 Explorer 16 Demo Board (see User's Guide for details) 3: The desired MCP46XX device (in MSOP package) must be soldered onto the extra board.
TABLE 10-2:
Application Note Number AN1080 AN737 AN692 AN691 AN219 -- --
TECHNICAL DOCUMENTATION
Title Understanding Digital Potentiometers Resistor Variations Using Digital Potentiometers to Design Low Pass Adjustable Filters Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect Optimizing the Digital Potentiometer in Precision Circuits Comparing Digital Potentiometers to Mechanical Potentiometers Digital Potentiometer Design Guide Signal Chain Design Guide Literature # DS01080 DS00737 DS00692 DS00691 DS00219 DS22017 DS21825
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NOTES:
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11.0
11.1
PACKAGING INFORMATION
Package Marking Information
Example: Part Number XXXX XYWW NNN MCP4531-502E/MF MCP4531-103E/MF MCP4531-104E/MF MCP4531-503E/MF MCP4551-502E/MF MCP4551-103E/MF MCP4551-104E/MF MCP4551-503E/MF Code DACA DACB DACD DACC DACT DACU DACW DACV Part Number MCP4532-502E/MF MCP4532-103E/MF MCP4532-104E/MF MCP4532-503E/MF MCP4552-502E/MF MCP4552-103E/MF MCP4552-104E/MF MCP4552-503E/MF Code DACE DACF DACH DACG DACX DACY DADA DACZ DACA E828 256
8-Lead DFN (3x3)
8-Lead MSOP XXXXXX YWWNNN
Part Number MCP4531-103E/MS MCP4531-104E/MS MCP4531-502E/MS MCP4531-503E/MS MCP4551-103E/MS MCP4551-104E/MS MCP4551-502E/MS MCP4551-503E/MS
Code 453113 453114 453152 453153 455113 455114 455152 455153
Part Number MCP4532-103E/MS MCP4532-104E/MS MCP4532-502E/MS MCP4532-503E/MS MCP4552-103E/MS MCP4552-104E/MS MCP4552-502E/MS MCP4552-503E/MS
Code 453213 453214 453252 453253 455213 455214 455252 455253
Example 453113 828256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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MCP453X/455X/463X/465X
Package Marking Information (Continued)
10-Lead DFN (3x3) Part Number XXXX YYWW NNN MCP4632-502E/MF MCP4632-103E/MF MCP4632-104E/MF MCP4632-503E/MF 10-Lead MSOP XXXXXX YWWNNN Part Number MCP4632-502E/UN MCP4632-103E/UN MCP4632-104E/UN MCP4632-503E/UN Code 463252 463213 463214 463253 Part Number MCP4652-502E/UN MCP4652-103E/UN MCP4652-104E/UN MCP4652-503E/UN Code 465252 465213 465214 465253 Code AABA AACA AAEA AADA Part Number MCP4652-502E/MF MCP4652-103E/MF MCP4652-104E/MF MCP4652-503E/MF Code AAKA AALA AAPA AAMA Example 463252 828256 AAFA 0828 256 Example:
14-Lead TSSOP (MCP4631, MCP4651)
Example
XXXXXXXX YYWW NNN
4631502E 0828 256
16-Lead QFN (MCP4631, MCP4651)
Example
XXXXX XXXXXX XXXXXX YYWWNNN
4631 502 e E/ML^^3 828256
DS22096A-page 72
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
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DS22096A-page 79
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MCP453X/455X/463X/465X
1RWH
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DS22096A-page 81
MCP453X/455X/463X/465X
NOTES:
DS22096A-page 82
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
APPENDIX A: REVISION HISTORY
Revision A (November 2008)
* Original Release of this Document.
(c) 2008 Microchip Technology Inc.
DS22096A-page 83
MCP453X/455X/463X/465X
NOTES:
DS22096A-page 84
(c) 2008 Microchip Technology Inc.
MCP453X/455X/463X/465X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XXX X /XX
Examples:
a) b) c) d) e) a) b) c) d) e) a) b) c) d) e) a) b) c) d) e) a) b) c) d) e) a) b) c) d) e) a) b) c) d) e) a) b) c) d) e) XX MCP4531-502E/XX: MCP4531-103E/XX: MCP4531-503E/XX: MCP4531-104E/XX: MCP4531T-104E/XX: MCP4532-502E/XX: MCP4532-103E/XX: MCP4532-503E/XX: MCP4532-104E/XX: MCP4532T-104E/XX: MCP4551-502E/XX: MCP4551-103E/XX: MCP4551-503E/XX: MCP4551-104E/XX: MCP4551T-104E/XX: MCP4552-502E/XX: MCP4552-103E/XX: MCP4552-503E/XX: MCP4552-104E/XX: MCP4552T-104E/XX: MCP4631-502E/XX: MCP4631-103E/XX: MCP4631-503E/XX: MCP4631-104E/XX: MCP4631T-104E/XX: MCP4632-502E/XX: MCP4632-103E/XX: MCP4632-503E/XX: MCP4632-104E/XX: MCP4632T-104E/XX: MCP4651-502E/XX: MCP4651-103E/XX: MCP4651-503E/XX: MCP4651-104E/XX: MCP4651T-104E/XX: MCP4652-502E/XX: MCP4652-103E/XX: MCP4652-503E/XX: MCP4652-104E/XX: MCP4652T-104E/XX: = = = = = 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device 10 k, 8-LD Device 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device
Resistance Temperature Package Version Range
Device:
MCP4531: MCP4531T: MCP4532: MCP4532T: MCP4551: MCP4551T: MCP4552: MCP4552T: MCP4631: MCP4631T: MCP4632: MCP4632T: MCP4651: MCP4651T: MCP4652: MCP4652T:
Single Non-Volatile 7-bit Potentiometer Single Non-Volatile 7-bit Potentiometer (Tape and Reel) Single Non-Volatile 7-bit Rheostat Single Non-Volatile 7-bit Rheostat (Tape and Reel) Single Non-Volatile 8-bit Potentiometer Single Non-Volatile 8-bit Potentiometer (Tape and Reel) Single Non-Volatile8-bit Rheostat Single Non-Volatile 8-bit Rheostat (Tape and Reel) Dual Non-Volatile 7-bit Potentiometer Dual Non-Volatile 7-bit Potentiometer (Tape and Reel) Dual Non-Volatile 7-bit Rheostat Dual Non-Volatile 7-bit Rheostat (Tape and Reel) Dual Non-Volatile 8-bit Potentiometer Dual Non-Volatile 8-bit Potentiometer (Tape and Reel) Dual Non-Volatile8-bit Rheostat Dual Non-Volatile 8-bit Rheostat (Tape and Reel)
Resistance Version:
502 = 5 k 103 = 10 k 503 = 50 k 104 = 100 k
Temperature Range:
E
= -40C to +125C
Package:
MF ML MS ST UN
= = = = =
Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead Plastic Quad Flat No-lead (QFN), 16-lead Plastic Micro Small Outline (MSOP), 8-lead Plastic Thin Shrink Small Outline (TSSOP), 14-lead Plastic Micro Small Outline (MSOP), 10-lead
MF for 8/10-lead 3x3 DFN ML for 16-lead QFN MS for 8-lead MSOP ST for 14-lead TSSOP UN for 10-lead MSOP
(c) 2008 Microchip Technology Inc.
DS22096A-page 85
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NOTES:
DS22096A-page 86
(c) 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2008 Microchip Technology Inc.
DS22096A-page 87
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/02/08
DS22096A-page 88
(c) 2008 Microchip Technology Inc.

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